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1 for more information www.linear.com/ltc2387-18 typical a pplica t ion fea t ures descrip t ion 18-bit, 15msps sar adc the lt c ? 2387-18 is a low noise, high speed, 18-bit 15msps successive approximation register (sar) adc ideally suited for a wide range of applications. the combination of excellent linearity and wide dynamic range makes the ltc2387 -18 ideal for high speed imaging and instru - mentation applications. no latency operation provides a unique solution for high speed control loop applications. the ver y low distortion at high input frequencies enables communications applications requiring wide dynamic range and significant signal bandwidth. to support high speed operation while minimizing the number of data lines, the ltc2387-18 features a serial lvds digital interface. the lvds interface has one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application. fft, f smpl = 15msps, f in = 2khz a pplica t ions n 15msps throughput rate n no pipeline delay, no cycle latency n 95.7db snr (typ) at f in = 1mhz n 102db sfdr (typ) at f in = 1mhz n nyquist sampling up to 7.5mhz input n guaranteed 18-bit, no missing codes n 3lsb inl (max) n 8.192v p-p differential inputs n 5v and 2.5v supplies n internal 20ppm/c (max) reference n serial lvds interface n 125mw power dissipation n 32-pin (5mm 5mm) qfn package n high speed data acquisition n imaging n communications n control loops n instrumentation n ate l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765, 8232905, 8810443. other patents are pending. sample clock 10f 0.1f 0.1f 2.5v 5v 0.1f 0.1f clk dco da db lvds interface 238718 ta01a in ? in + 82pf 24.9 24.9 gnd refin refbuf refgnd ltc2387-18 v cm 82pf twolanes testpat pd cnv v dd 2.5v 0.1f v ddl ov dd + ? 4.096v 0v 4.096v 0v lt c2387 -18 238718fa 7.5 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 snr = 96.0db amplitude (dbfs) f in = 2khz 238718 ta01b thd = ?117db sinad = 95.7db sfdr = 119db frequency (mhz) 0 2.5 5
2 for more information www.linear.com/ltc2387-18 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v dd ) .................................................. 6v su pply voltage (v ddl , ov dd ) ................................... 2.8 v analog input voltage (note 3) in + , in C ......................... (gn d C 0.3v ) to (v dd + 0.3v ) refbuf ......................... (g nd C 0.3v ) to (v dd + 0.3v ) refin (note 4) ........................... (gn d C 0.3v ) to 2.8v digital input voltage (note 3) pd , testpat ............. (gn d C 0.3v ) to (ov dd + 0.3v ) clk + , clk C ................ (gn d C 0.3v ) to (ov dd + 0.3v ) twolanes, cnv + , cnv C ........................... (gn d C 0.3v ) to (v ddl + 0.3v ) power dissipation .............................................. 5 00mw operating temperature range lt c2387 c ................................................ 0c to 70 c lt c 2387 i ............................................. C 40 c to 85 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) 32 33 gnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1gnd in + in ? gnd refgnd refgnd refbuf refbuf clk + clk ? ov dd gnd dco + dco ? da + da ? v cm v ddl v ddl gnd cnv + cnv ? gnd twolanes refin gnd v dd v dd pd testpat db ? db + t jmax = 125c, ja = 34c/w exposed pad (pin 33) is gnd, must be soldered to pcb o r d er i n f or m a t ion e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) lead free finish tape and reel part marking* package description temperature range ltc2387cuh-18#pbf ltc2387cuh-18#trpbf 238718 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2387iuh-18#pbf ltc2387iuh-18#trpbf 238718 32-lead (5mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 6) l C0.1 v refbuf + 0.1 v v in C absolute input range (in C ) (note 6) l C0.1 v refbuf + 0.1 v v in + C v in C input differential voltage range v in + C v in C l Cv refbuf v refbuf v v incm common mode input range (v in + + v in C )/2 l v refbuf /2 C 0.1 v refbuf /2 v refbuf /2 + 0.1 v i in analog input dc leakage current l C1 1 a c in analog input capacitance sample mode hold mode 20 2 pf pf cmrr input common mode rejection ratio f in = 1mhz 75 db lt c2387 -18 238718fa
3 for more information www.linear.com/ltc2387-18 c onver t er c harac t eris t ics dyna m ic a ccuracy i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 5, 10) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units resolution l 18 bits no missing codes l 18 bits transition noise 1.4 lsb rms inl integral linearity error refbuf = 4.096v (notes 7, 9) l C3 0.6 3 lsb dnl differential linearity error l C0.9 0.2 0.9 lsb zse zero-scale error (note 8) l C16 1.5 16 lsb zero-scale error drift 0.02 lsb/c fse full-scale error refbuf = 4.096v (refbuf overdriven) (notes 8, 9) refin = 2.048v (refin overdriven) (note 8) l l C25 C160 5 25 25 160 lsb lsb full-scale error drift refbuf = 4.096v (refbuf overdriven) (note 9) refin = 2.048v (refin overdriven) 0.1 1.5 ppm/c ppm/c symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 2khz f in = 1mhz f in = 5mhz l l 93 92.6 95.7 94.5 83 db db db snr signal-to-noise ratio f in = 2khz f in = 1mhz f in = 5mhz l l 93.2 93 96 95.7 94.6 db db db thd t otal harmonic distortion (first five harmonics) f in = 2khz f in = 1mhz f in = 5mhz l l C117 C101 C83 C 103 C96 db db db sfdr spurious free dynamic range f in = 2khz f in = 1mhz f in = 5mhz l l 103 97 119 102 84 db db db C 3db input bandwidth 200 mhz symbol parameter conditions min typ max units v refin internal reference output voltage i out = 0a 2.043 2.048 2.053 v v refin temperature coefficient (note 11) l 5 20 ppm/c refin output impedance 15 k v refin line regulation v dd = 4.75v to 5.25v 0.3 mv/v refin input voltage range (refin overdriven) (note 6) l 2.008 2.048 2.088 v lt c2387 -18 238718fa
4 for more information www.linear.com/ltc2387-18 r e f erence b u ff er c harac t eris t ics digi t al i npu t s an d digi t al o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v refbuf reference buffer output voltage v refin = 2.048v l 4.090 4.096 4.102 v refbuf input voltage range (refbuf overdriven) (notes 6, 9) l 4.016 4.096 4.176 v i refbuf refbuf load current v refbuf = 4.096v (refbuf overdriven) (notes 9, 12) v refbuf = 4.096v, sleep mode (refbuf overdriven) (note 9) l 1.6 0.5 1.8 ma ma v cm common mode output v refbuf = 4.096v, i out = 0a l 2.028 2.048 2.068 v v cm output impedance C1ma < i out < 1ma 15 symbol parameter conditions min typ max units pd , testpat, twolanes v ih high level input voltage v ddl = ov dd = 2.5v l 1.7 v v il low level input voltage v ddl = ov dd = 2.5v l 0.6 v i in digital input current v in = 0v to 2.5v l C10 10 a c in digital input capacitance 3 pf cnv + , single-ended convert start mode (cnv C tied to gnd) v ih high level input voltage v ddl = 2.5v l 1.7 v v il low level input voltage v ddl = 2.5v l 0.6 v c in digital input capacitance 2 pf cnv + /cnv C , differential convert start mode v id differential input voltage (note 13) l 175 350 650 mv v icm common mode input voltage l 0.8 1.25 1.7 v clk + /clk C (lvds clock input) v id differential input voltage (note 13) l 175 350 650 mv v icm common mode input voltage l 0.8 1.25 1.7 v dco + /dco C , da + /da C , db + /db C (lvds outputs) v od differential output voltage 100 differential load l 247 350 454 mv v os common mode output voltage 100 differential load l 1.125 1.25 1.375 v symbol parameter conditions min typ max units v dd supply voltage (note 6) l 4.75 5 5.25 v v ddl supply voltage (note 6) l 2.375 2.5 2.625 v ov dd supply voltage (note 6) l 2.375 2.5 2.625 v i vdd i vddl i ovdd i powerdown i powerdown supply current supply current supply current power-down mode current power-down mode current 15msps sample rate 15msps sample rate 15msps sample rate power -down mode (i vdd ) power-down mode (i vddl + i ovdd ) l l l l l 5 31.4 8.8 1 2 6 35 10.3 20 250 ma ma ma a a p d power dissipation power-down mode 15msps sample rate power -down mode (i vdd + i vddl + i ovdd ) l l 125 10 144 725 mw w i diffcnv increase in i vddl with differential cnv mode enabled (no increase during power-down) 2.1 ma i twolane increase in i ovdd with two-lane mode enabled (no increase during power-down) 3.6 ma lt c2387 -18 238718fa
5 for more information www.linear.com/ltc2387-18 a d c ti m ing c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above v dd , v ddl or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above v dd , v ddl or ov dd without latchup. note 4: when this pin voltage is taken below ground, it will be clamped by an internal diode. when this pin voltage is taken above v ddl , it is clamped by a diode in series with a 2k resistor. this product can handle input currents up to 100ma below ground without latchup. note 5: v dd = 5v, v ddl = 2.5v, ov dd = 2.5v, f smpl = 15mhz, refin?=?2.048v, single-ended cnv, one-lane output mode unless otherwise noted. note 6: recommended operating conditions. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units f smpl sampling frequency l 0.02 15 msps t conv cnv to output data ready l 54 58 63 ns t acq acquisition time t cyc C 39 ns t cyc time between conversions l 66.6 50,000 ns t cnvh cnv high time (note 13) l 5 ns t cnvl cnv low time (note 13) l 8 ns t firstclk cnv to first clk from the same conversion (note 13) l 65 ns t lastclk cnv to last clk from the previous conversion (note 13) l 49 ns t clkh clk high time l 1.25 ns t clkl clk low time l 1.25 ns t clkdco clk to dco delay (note 13) l 0.7 1.3 2.3 ns t clkd clk to da/db delay (note 13) l 0.7 1.3 2.3 ns t skew dco to da/db skew t clkd C t clkdco (note 13) l C200 0 200 ps t ap sampling delay time (note 13) 0 ns t jitter sampling delay jitter (note 13) 0.25 ps rms note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 00 0000 0000 0000 0000 and 11?1111 1111 1111 1111. full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. note 9: when refbuf is overdriven, the internal reference buffer must be turned off by setting refin = 0v. note 10: all specifications in db are referred to a full-scale v refbuf differential input. note 11: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 12: f smpl = 15mhz, i refbuf varies linearly with sample rate. note 13: guaranteed by design, not subject to test. lt c2387 -18 238718fa
6 for more information www.linear.com/ltc2387-18 typical p er f or m ance c harac t eris t ics 32k point fft f smpl = 15msps, f in = 2khz 32k point fft f smpl = 15msps, f in = 200khz 32k point fft f smpl = 15msps, f in = 1mhz 32k point fft f smpl = 15msps, f in = 5mhz snr, sinad vs input frequency integral nonlinearity vs output code (lsb) differential nonlinearity vs output code dc histogram t a = 25c, v dd = 5v, v ddl = 2.5v, ov dd = 2.5v, refin = 2.048v, f smpl = 15msps, unless otherwise noted. integral nonlinearity vs output code (ppm) output code ?1.0 dnl error (lsb) 0.8 0.6 0.4 0.2 0.0 ?0.8 ?0.6 ?0.4 ?0.2 1.0 238718 g02 0 65536 131072 196608 262144 output code 0 counts 30000 10000 70000 40000 20000 50000 60000 80000 238718 g03 n-6 n-4 n-5 n-1 n-3 n-2 n n+2 n+1 n+4 n+3 n+6 n+5 frequency (mhz) 0 2.5 5.0 7.5 ?160 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 0 238718 g05 lt c2387 -18 238718fa ?1.0 in 238718 g07 snr sinad frequency (mhz) 0.01 0.1 1 10 78.0 ?0.5 80.0 82.0 84.0 86.0 88.0 90.0 92.0 94.0 96.0 98.0 0 snr, sinad (dbfs) 238718 g08 0.5 1.0 1.5 2.0 inl error (lsb) 238718 g01a output code output code 0 65536 131072 196608 262144 ?6.0 ?4.5 ?3.0 ?1.5 0 0 1.5 3.0 4.5 6.0 inl error (ppm) 238718 g01b snr = 96.0db thd = ?117db sinad = 95.7db sfdr = 119db 65536 frequency (mhz) 0 2.5 5 7.5 ?160 ?140 ?120 ?100 ?80 131072 ?60 ?40 ?20 0 amplitude (dbfs) f in = 2khz 238718 g04 snr = 95.8db thd = ?109db sinad = 95.6db 196608 sfdr = 109db snr = 95.6db thd = ?103db sinad = 94.6db sfdr = 104db frequency (mhz) 0 2.5 5 7.5 262144 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) ?2.0 238718 g06 snr = 94.6db thd = ?83db sinad = 83db sfdr = 84db frequency (mhz) 0 2.5 5 7.5 ?1.5 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs)
7 for more information www.linear.com/ltc2387-18 typical p er f or m ance c harac t eris t ics snr, sinad vs temperature, f in = 2khz, C1dbfs thd, harmonics vs temperature, f in = 2khz, C1dbfs inl/dnl vs temperature full-scale error vs temperature, refbuf = 4.096v zero-scale error vs temperature supply current vs temperature sfdr vs input level, f in = 2khz sfdr vs input level, f in = 1mhz thd vs input frequency and amplitude t a = 25c, v dd = 5v, v ddl = 2.5v, ov dd = 2.5v, refin = 2.048v, f smpl = 15msps, unless otherwise noted. lt c2387 -18 238718fa 10 0 20 40 60 80 ?130 ?125 ?120 ?115 ?110 ?140 thd, harmonics (dbfs) f in = 2khz, -1dbfs 238718 g13 max inl max dnl min dnl min inl temperature (c) ?40 ?20 ?130 0 20 40 60 80 ?1.00 ?0.75 ?0.50 ?0.25 0 ?120 0.25 0.50 0.75 1.00 inl/dnl error (lsb) 238718 g14 temperature (c) ?40 ?20 0 ?110 20 40 60 80 ?6 ?4 ?2 0 2 4 ?100 6 full-scale error (lsb) refbuf = 4.096v 238718 g15 + fs ? fs temperature (c) ?40 ?20 0 ?90 20 40 60 80 ?6 ?4 ?2 0 2 4 ?80 6 zero-scale error (lsb) zero-scale error vs temperature 238718 g16 i vddl i vdd i ovdd temperature (c) ?40 ?20 ?70 0 20 40 60 80 0 5 10 15 20 thd (dbfs) 25 30 35 supply current (ma) supply current vs temperature 238718 g17 ?1dbfs and amplitude 238718 g09 input level (dbfs) ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?3dbfs ?10 0 50 60 70 80 90 100 110 120 ?6dbfs 130 140 150 sfdr (dbfs, dbc) in 238718 g10 dbc dbfs input level (dbfs) ?80 ?10dbfs ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 60 frequency (mhz) 70 80 90 100 110 120 130 140 150 sfdr (dbfs, dbc) 0.01 f in = 1mhz 238718 g11 dbc dbfs snr sinad temperature (c) ?40 ?20 0 0.1 20 40 60 80 92 93 94 95 96 97 1 98 snr, sinad (dbfs) in 238718 g12 thd 2nd 3rd temperature (c) ?40 ?20
8 for more information www.linear.com/ltc2387-18 typical p er f or m ance c harac t eris t ics supply current vs sample rate analog input current vs differential input voltage internal reference output vs temperature t a = 25c, v dd = 5v, v ddl = 2.5v, ov dd = 2.5v, refin = 2.048v, f smpl = 15msps, unless otherwise noted. p in func t ions gnd (pins 1, 4, 10, 21, 26, 29 ): ground. connect to a solid ground plane in the pcb underneath the adc. in + , in C (pins 2, 3): positive and negative differential analog inputs. the inputs must be driven differentially and 180 out of phase, with a common mode voltage of 2.048v. the differential input range is 4.096v (each input pin swings from 0v to 4.096v.) refgnd (pins 5, 6): reference ground. the two pins should be shorted together and connected to the refer - ence bypass capacitor with a short, wide trace. in ad - dition, connect the pins to the exposed pad (pin 33). a suggested layout is shown in the adc reference section of the data sheet. refbuf (pins 7, 8) : internal reference buffer output. the output voltage of the internal 2 gain reference buffer, nominally 4.096v , is provided on this pin. the two pins should be shorted together and bypassed to refgnd with a 10f (x7r, 0805 size) ceramic capacitor. if the internal buffer is not required, tie refin to gnd to power down the buffer and connect an external 4.096v reference to refbuf. refin (pin 9) : internal reference output/reference buffer input. the output voltage of the internal reference, nomi - nally 2.048v, is output on this pin. an external reference can be applied to refin if a more accurate reference is required. for increased filtering of reference noise, bypass this pin to gnd using a 0.1f or larger ceramic capacitor. if the internal reference buffer is not used, tie refin to gnd to power down the buffer and connect an external buffered reference to refbuf. lt c2387 -18 238718fa 0 5 10 15 20 25 30 35 supply current (ma) 238718 g18 i vddl in ? in + f smpl = 15msps differential input (v) ?4.096 ?2.048 0 2.048 4.096 ?1.00 i vdd ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 analog input current (ma) differential input voltage i ovdd 238718 g19 three typical units temperature (c) ?40 ?20 0 20 40 60 80 sample rate (msps) 2.047 2.048 2.049 2.050 reference output (v) 238718 g20 0 5 10 15
9 for more information www.linear.com/ltc2387-18 p in func t ions v dd (pins 11, 12): 5v analog power supply. the range of v dd is 4.75v to 5.25v. the two pins should be shorted together and bypassed to gnd with 0.1f and 10f ce- ramic capacitors. pd (pin 13) : digital input that enables power-down mode. when pd is low, the ltc2387 enters power-down mode, and all circuitry (including the lvds interface) is shut down. when pd is high, the part operates normally. logic levels are determined by ov dd . testpat (pin 14) : digital input that forces the lvds data outputs to be a test pattern. when testpat is high, the digital outputs are a test pattern. when testpat is low, the digital outputs are the adc conversion result. logic levels are determined by ov dd . db C /db + , da C /da + (pins 15/16, 17/18): serial lvds data outputs. in one-lane output mode, db C /db + are not used and their lvds driver is disabled to reduce power consumption. dco C /dco + (pins 19/20): lvds data clock output. this is an echoed version of clk C /clk + that can be used to latch the data outputs. ov dd (pin 22): 2.5v output power supply. the range of ov dd is 2.375v to 2.625v. bypass to gnd with a 0.1f ceramic capacitor. clk C /clk + (pins 23/24): lvds clock input. this is an externally applied clock that serially shifts out the conver - sion result. t wolanes (pin 25) : digital input that enables two-lane output mode. when twolanes is high (two-lane output mode), the adc outputs two bits at a time on da C /da + and db C /db + . when twolanes is low (one-lane output mode), the adc outputs one bit at a time on da C /da + , and db C /db + are disabled. logic levels are determined by v ddl . cnv C /cnv + (pins 27/28): conversion start lvds input. a rising edge on cnv + puts the internal sample-and-hold into the hold mode and starts a conversion cycle. cnv + can also be driven with a 2.5v cmos signal if cnv C is tied to gnd. v ddl (pins 30, 31): 2.5v analog power supply. the range of v ddl is 2.375v to 2.625v . the two pins should be shorted together and bypassed to gnd with 0.1f and 10f ceramic capacitors. v cm (pin 32): common mode output. v cm , nominally 2.048v, can be used to set the common mode of the ana - log inputs. bypass to gnd with a 0.1f ceramic capacitor close to the pin. if v cm is not used, the bypass capacitor is not necessary as long as the parasitic capacitance on the v cm pin is under 10pf. exposed pad (pin 33): the exposed pad on the bottom of the package. connect to the ground plane of the pcb using multiple vias. lt c2387 -18 238718fa
10 for more information www.linear.com/ltc2387-18 func t ional b lock diagra m serial lvds interface clk dco da db 238718 bd in ? in + v dd v ddl ov dd v cm refgnd refbuf refin gnd control logic cnv twolanes testpat pd ? + 18-bit, 15msps adc 0.5 2 2.048v reference 15k lt c2387 -18 238718fa
11 for more information www.linear.com/ltc2387-18 ti m ing diagra m t ap t cnvh analog input cnv ? cnv + d17 16 15 14 13 12 11 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 output data from sample n logic 0 d17 16 15 14 13 12 11 10 d9 d8 d7 logic 0 d8 d7 d6 d5 d4 d3 d2 d1 d0 output data from sample n+1 output data from sample n?1 sample n sample n+1 clk + clk ? dco + dco ? da + da ? input acquisition input acquisition t acq t cyc 1 2 3 4 5 6 7 8 9 t lastclk t firstclk t conv 238718 td01 one-lane output mode lt c2387 -18 238718fa
12 for more information www.linear.com/ltc2387-18 ti m ing diagra m t ap t cnvh analog input cnv ? cnv + d17 15 13 11 d9 d7 d5 d3 d1 logic 0 d17 15 13 11 d9 logic 0 15 13 11 d9 d7 d5 d3 d1 sample n sample n+1 clk + clk ? dco + dco ? da + da ? input acquisition input acquisition t acq t cyc 1 2 3 4 5 t lastclk t firstclk t conv d16 14 12 10 d8 d6 d4 d2 d0 logic 0 d16 14 12 10 d8 logic 0 14 12 10 d8 d6 d4 d2 d0 output data from sample n output data from sample n+1 238718 td02 output data from sample n?1 db + db ? two-lane output mode lt c2387 -18 238718fa
13 for more information www.linear.com/ltc2387-18 ti m ing diagra m a pplica t ions i n f or m a t ion data output timing t clkh t clkdco clk + clk ? dco + dco ? da + da ? t clkdco t clkd t clkd t clkl 238718 td03 db + db ? o verview the ltc2387 -18 is a low noise, high speed, 18-bit succes - sive approximation register (sar) adc. operating from 5v and 2.5v supplies, the ltc2387 -18 has a fully differential 4.096v input range, making it ideal for applications that require a wide dynamic range. the ltc2387-18 achieves 3lsb inl (maximum), no missing codes at 18-bits and 96db snr (typical). the ltc2387 -18 includes a precision internal 2.048v reference, with a guaranteed 0.25% initial accuracy and a 20ppm/ c (maximum) temperature coefficient, as well as an internal reference buffer. the ltc2387 -18 also has a high speed serial lvds interface that can output one or two bits at a time. the fast 15msps throughput with no pipeline latency makes the ltc2387 -18 ideally suited for a wide variety of high speed applications. the ltc2387-18 dissipates only 125mw at 15msps and has a power-down mode to reduce the power consumption to 10w during inactive periods. c onver ter o pera tion the ltc2387 -18 operates in two phases. during the ac - quisition phase, the sample capacitors are connected to the analog input pins in + and in C to sample the differential analog input voltage. a rising edge on the cnv pin initiates a conversion. during the conversion phase, the adc is sequenced through a successive approximation algorithm, comparing the sampled input with binary-weighted frac - tions of the reference voltage (e.g. v refbuf /2, v refbuf /4 v refbuf /262144) using a differential comparator. at the end of conversion, control logic prepares the 18-bit digital output code for serial transfer. t ransfer f unction the ltc2387 -18 digitizes the full-scale voltage of 2 refbuf into 2 18 levels, resulting in an lsb size of 31.25v with refbuf = 4.096v. the output data is in twos complement format. the ideal transfer function is shown in figure?1. the ideal offset binary transfer func - tion can be obtained from the twos complement transfer function by inverting the most significant bit (msb) of each output code. lt c2387 -18 238718fa
14 for more information www.linear.com/ltc2387-18 a pplica t ions i n f or m a t ion a nalog i nputs the ltc2387 -18 has a fully differential 4.096v input range. the in + and in C pins should be driven 180 degrees out-of-phase with respect to each other, centered around a common mode voltage (in + + in C )/2 that is restricted to (v refbuf /2 0.1v ). the adc samples and digitizes the voltage difference between the two analog input pins (in + ? in C ), and any unwanted signal that is common to both inputs is reduced by the common mode rejection ratio (cmrr) of the adc. the analog inputs can be modeled by the equivalent circuit shown in figure 2. the diodes and 10 resistors at the input provide esd and overdrive protection. in the acquisition phase, each input sees ap - proximately 18pf (c sample ) from the sampling capacitor in series with 28 (r on ) from the on-resistance of the sampling switch. c par is a lumped capacitance on the order of 2pf formed primarily of diode junctions. the inputs draw a small current spike while charging the c sample capacitors during acquisition. this current spike is consistent and does not depend on the previously sampled input voltage. during conversion and power-down, the analog inputs draw only a small leakage current. input drive circuits a low impedance source can directly drive the high im - pedance inputs of the ltc2387 -18 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis - tortion performance of the adc. minimizing settling time is important even for dc signals because the adc inputs draw a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2387-18. the ampli - fier provides low output impedance enabling fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the current spike drawn by the adc inputs when entering acquisition. the ltc2387 -18 is optimized for pulsed inputs that are fully settled when sampled, or dynamic signals up to the nyquist frequency (7.5mhz). input signals that change faster than 300mv/ns when they are sampled are not recommended. this is equivalent to an 8v p-p sine wave at 12mhz. input filtering the noise and distortion of the buffer amplifier and other supporting circuitry must be considered since they add to the adc noise and distortion. a buffer amplifier with low noise density must be selected to minimize snr degradation. a filter network should be placed between the buffer output and adc input to both minimize the noise contribution of the buffer and reduce disturbances reflected into the buffer from adc sampling transients. a simple one-pole lowpass rc filter is sufficient for many applications. it is important that the rc time constant of this filter be small enough to allow the analog inputs to settle within the adc acquisition time (t acq ), as insufficient settling can limit inl and thd performance. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. figure 1. ltc2387-18 transfer function figure 2. equivalent circuit for the differential analog inputs of the ltc2387-18 input voltage (v) 0v output code (two?s complement) ?1 lsb 238718 f01 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/262144 in + 10 c par 2pf c sample 18pf v dd 238718 f02 in ? bias voltage 10 c par 2pf c sample 18pf v dd 28 28 lt c2387 -18 238718fa
15 for more information www.linear.com/ltc2387-18 a pplica t ions i n f or m a t ion npo type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. figure 3 shows a typical input drive circuit with an rc filter. the optimal values for r and c are application-specific and may require experimentation. setting r = 24.9? gives good performance over a wide range of conditions. input currents one of the biggest challenges in coupling an amplifier to the ltc2387 -18 is in dealing with current spikes drawn by analog inputs at the start of each acquisition phase. the analog inputs may be modeled as a switched capacitor load on the drive circuit. a drive circuit may rely partially on attenuating switched-capacitor current spikes with small filter capacitors placed directly at the adc inputs and par - tially on the driver amplifier having sufficient bandwidth to recover from the residual disturbance. amplifiers optimized for dc per formance may not have sufficient bandwidth to fully recover at the adcs maximum conversion rate, which can produce nonlinearity and other errors. coupling filter circuits may be classified in two broad categories: fully settled C this case is characterized by filter time constants and an overall settling time that are consider - ably shorter than the sample period. when acquisition begins, the coupling filter is disturbed. for a typical first order rc filter , the disturbance will look like an initial step with an exponential decay . the amplifier will have its own response to the disturbance, which may include ringing. if the input settles completely (to within the accuracy of the ltc2387 -18), the disturbance will not contribute any error. partially settled C in this case, the beginning of acquisi - tion causes a disturbance of the coupling filter, which then begins to settle out towards the nominal input voltage. however , acquisition ends (and the conversion begins) before the input settles to its final value. this generally produces a gain error , but as long as the settling is linear, no distortion is produced. the coupling filters response is affected by the amplifier s output impedance and other parameters. a linear settling response to fast switched- capacitor current spikes can not always be assumed for precision, low bandwidth amplifiers. the coupling filter serves to attenuate the current spikes high-frequency energy before it reaches the amplifier. figure 3. typical input drive circuit figure 4. suggested range of c filt values vs sample rate the value for c filt involves a trade off: larger values give better noise, and smaller values give better full-scale error. figure 4 shows a range of capacitor values to consider as a starting point based on the sample rate. lt c2387 -18 238718fa 4.096v 0v in + in ? ltc2387-18 238718 f03 max value (lower noise) min value (lower full?scale error) sample rate (msps) 9 24.9 10 11 12 13 14 15 50 100 150 200 24.9 250 300 350 400 c filt (pf) 238718 f04 c filt c filt 4.096v 0v
16 for more information www.linear.com/ltc2387-18 figure 6. configuration for using the internal reference figure 5. ltc2387-18 internal reference circuitry adc r eference the internal reference circuitr y of the ltc2387 -18 is shown in figure 5. there is a low noise, low drift (20ppm/c), bandgap reference connected to refin (pin 9). an internal reference buffer gains the refin voltage by 2 to 4.096v at refbuf (pins 7, 8). the voltage difference between refbuf and refgnd determines the full-scale input range of the adc. the reference and reference buffer can also be externally driven if desired. internal reference with internal reference buffer to use the internal reference and internal reference buf - fer, bypass refin to gnd with a 0.1f ceramic capacitor (figure 6). bypass refbuf to refgnd with a single 10f (x7r, 0805 size) ceramic capacitor . the refbuf capacitor should be as close as possible to the ltc2387-18 package to minimize wiring inductance. do not place this capaci - tor on the opposite side of the board. adding a second, smaller capacitor in parallel with the 10f may degrade performance and is not recommended. figure 7 shows a suggested layout for the refbuf capaci - tor. the capacitor should be connected to refbuf and refgnd through short, wide traces. refgnd should also be connected with a wide trace to the grounded exposed pad (pin 33). 238718 f07 9 10 11 12 8 7 6 5 4 3 2 1 a pplica t ions i n f or m a t ion figure 7. suggested refbuf bypass capacitor layout 238718 f05 2.048v reference adc core refgnd refbuf refin 8k 15k 9 8 7 6 5 ltc2387-18 2 238718 f06 refgnd refbuf refin 0.1f ltc2387-18 refgnd refbuf 10f lt c2387 -18 238718fa
17 for more information www.linear.com/ltc2387-18 a pplica t ions i n f or m a t ion figure 9. overdriving refbuf using the ltc6655-4.096 external reference with internal reference buffer if more accuracy and/or lower drift is desired, refin can be directly overdriven by an external 2.048v reference as shown in figure 8. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power, and high accuracy, the ltc6655-2.048 is well suited for use with the ltc2387-18 when overdriving the internal ref - erence. the ltc6655-2.048 offers 0.025% (max) initial accuracy and 2ppm/ c (max) temperature coefficient for high precision applications. bypassing the ltc6655-2.048 with a 2.7f to 10f ceramic capacitor close to the refin pin is recommended. external reference buffer the internal reference buffer can also be overdriven with an external 4.096v reference at refbuf as shown in figure 9. to do so, refin must be grounded to disable the reference buffer. the external reference must have a fast transient response and be able to drive the 0.5ma to 1.6ma load at the refbuf pin. the ltc6655-4.096 is recommended when overdriving refbuf. common mode output the v cm pin is an output that provides one-half the voltage present on the refbuf pin. this voltage can be used to set the common mode of a differential amplifier driving the analog inputs. bypass v cm to gnd with a 0.1f ceramic capacitor. if v cm is not used it can be left floating, but the parasitic capacitance on the pin needs to be under 10pf. the v cm output has 1/f noise which for most driver circuits will be removed by the adc common mode rejection ratio. v cm is not recommended for single-ended to differential circuits that pass the v cm noise to only one adc input. d ynamic p erformance fast fourier transform (ff t) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the ltc2387-18 provides guaranteed tested limits for both ac distortion and noise measurements. figure 8. using the ltc6655-2.048 as an external reference 238718 f09 refgnd refbuf refin ltc2387-18 refgnd refbuf 10f v in 5v ltc6655-4.096 gnd shdn v out_f v out_s 0.1f 238718 f08 refgnd refbuf refin 2.7f ltc2387-18 refgnd refbuf 10f v in 5v ltc6655-2.048 gnd shdn v out_f v out_s 0.1f lt c2387 -18 238718fa
18 for more information www.linear.com/ltc2387-18 figure 10. 32k point fft of the ltc2387 - 18, f smpl = 15msps, f in = 2khz a pplica t ions i n f or m a t ion signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 10 shows that the ltc2387-18 achieves a typical sinad of 95.7db at a 15mhz sampling rate with a 2khz input. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 10 shows that the ltc2387-18 achieves a typical snr of 96db at a 15mhz sampling rate with a 2khz input. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics. figure 10 shows that the ltc2387-18 achieves a typical thd of C117db at a 15mhz sampling rate with a 2khz input. p ower c onsidera tions the ltc2387 -18 requires three power supplies: v dd (5v), v ddl (2.5v), and ov dd (2.5v). bypass v dd to gnd with a 0.1f ceramic capacitor close to the pair of pins and a 10f ceramic capacitor in parallel. bypass v ddl to gnd with a 0.1f ceramic capacitor close to the pair of pins and a 10f ceramic capacitor in parallel. ov dd can come from the same source as v ddl but it should be isolated by a ferrite bead and have its own 0.1f bypass capacitor. power supply sequencing the ltc2387 -18 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2387-18 has a power-on-reset (por) circuit that will reset the ltc2387 -18 at initial power-up or whenever v dd or v ddl drops well below their minimum values. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. lt c2387 -18 238718fa 7.5 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 snr = 96.0db amplitude (dbfs) f in = 2khz 238718 f10 thd = ?117db sinad = 95.7db sfdr = 119db frequency (mhz) 0 2.5 5
19 for more information www.linear.com/ltc2387-18 a pplica t ions i n f or m a t ion power-down mode when pd is pulled low, ltc2387 -18 enters power-down mode. in this state, all internal functions, including the reference and lvds outputs, are turned off and subsequent conversion requests are ignored. the power consumption drops to a typical value of 10w. this mode can be used if the ltc2387-18 is inactive for a long period of time and the user wants to minimize power dissipation. the amount of time required to recover from power-down mode depends on how refbuf is configured. when using the internal reference buffer with a 10f bypass capacitor, the adc will stabilize after 20ms. if refbuf is externally driven, the recovery time can be significantly less. t iming and c ontrol cnv timing the ltc2387-18 conversion is controlled by the cnv + and cnv C inputs. cnv + /cnv C can be driven directly with an lvds signal. alternatively, cnv + can be driven with a 0v to 2.5v cmos signal when cnv C is tied to gnd. a rising edge on cnv + will sample the analog inputs and start a conversion. the pulse width of cnv + should meet the t cnvh and t cnvl specifications in the timing table. after the ltc2387 -18 is powered on, or exits power-down mode, conversion data is invalid for the first two conver - sion cycles. subsequent results are accurate as long as the time between conversions meets the t cyc specification. if the analog input signal has not completely settled when it is sampled, the adc noise performance will be affected by jitter on the rising edge of cnv + . in this case the rising figure 11. digital output interface to an fpga edge of cnv + should be driven by a clean low jitter signal. note that the adc is less sensitive to jitter on the falling edge of cnv + . in applications that are insensitive to jitter, cnv can be driven directly from an fpga. internal conversion clock the ltc2387 -18 has an internal clock that is trimmed to achieve a maximum conversion time of 63ns . with a typical acquisition time of 27.7ns , throughput perfor - mance of 15msps is guaranteed. d igit al i nterf ace the ltc2387 -18 has a serial lvds digital interface that is easy to connect to an fpga. three lvds pairs are re - quired: clk , dco , and da . a fourth lvds pair, db , is optional (figure 11). 238718 f11 ltc2387-18 optional fpga 100 clk + clk ? ? + 100 dco + dco ? + ? 100 da + da ? 100 db + db ? + ? + ? lt c2387 -18 238718fa
20 for more information www.linear.com/ltc2387-18 figure 12. timing diagram for a single conversion in one-lane mode t conv 238718 f12 cnv d17 16 15 14 13 12 11 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clk dco da 1 2 3 4 5 6 7 8 9 msb lsb a pplica t ions i n f or m a t ion figure 13. valid time window for clocking out data t firstclk t lastclk 238718 f13 cnv clk 1 2 3 4 5 6 7 8 9 time window for clocking out conversion n conversion n conversion n+1 the lvds signals should be routed on the pc board as 100 differential transmission lines and terminated at the receiver with 100 resistors. a conversion is started by the rising edge of cnv + . when the conversion is complete, the most-significant data bit is output on da . data is then ready to be shifted out by applying a burst of nine clock pulses to the clk input. the data on da is updated by every edge of clk . an echoed version of clk is output on dco . the edges of da and dco are aligned, so dco can be used to latch da in the fpga. the timing of a single conversion is shown in figure 12. data must be clocked out after the current conversion is complete, and before the next conversion finishes. the valid time window for clocking out data is shown in figure 13. note that it is allowed to be still clocking out data when the next conversion begins. two-lane output mode at high sample rates the required lvds interface data rate can reach >400mbps. most fpgas can support this, but if a lower data rate is desired, the two-lane output mode can be used. when the twolanes input pin is tied high, lt c2387 -18 238718fa
21 for more information www.linear.com/ltc2387-18 the optional lvds output db is enabled, and data is out - put two bits at a time on da and db . enabling the db output increases the supply current from ov dd by about 3.6ma . in two-lane mode, five clock pulses are required for clk (see timing diagrams). output test patterns to allow in-circuit testing of the digital interface to the adc, there is a test mode that forces the adc data outputs to known values: one-lane mode: 10 1000 0001 1111 1100 two-lane mode: 11 0011 0000 1111 1100 the test pattern is enabled when the testpa t pin is brought high. b oard l a yout the ltc2387 -18 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , v ddl , ov dd , v cm , refin, and refbuf pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended (except for refbuf). the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. of particular importance is the capacitor between refbuf and refgnd, which should be a 10f (x7r, 0805 size) ceramic capacitor. this capacitor should be on the same side of the circuit board as the adc, and as close to the device as possible. adding a second, smaller capacitor in parallel with the 10f may degrade performance and is not recommended. the analog inputs, convert start, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. exposed package pad for good electrical and thermal performance, the exposed pad on the bottom of the package must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. mechanical stress shift the mechanical stress of mounting a part to a board can cause subtle changes to the snr and internal voltage reference. the best soldering method is to use ir reflow or convection soldering with a controlled temperature profile. hand soldering with a heat gun or a soldering iron is not recommended. a pplica t ions i n f or m a t ion lt c2387 -18 238718fa
22 for more information www.linear.com/ltc2387-18 p ackage descrip t ion please refer to http://www.linear.com/product/ltc2387-18#packaging for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) lt c2387 -18 238718fa
23 for more information www.linear.com/ltc2387-18 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 10/15 updated typical application, graph 4 and figure 10 fft plots. 1, 6, 18 lt c2387 -18 238718fa
24 for more information www.linear.com/ltc2387-18 ? linear technology corporation 2015 lt 1015 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2387-18 r ela t e d p ar t s typical a pplica t ion part number description comments adcs ltc2378-20 20-bit, 1msps, low power sar adc 104db snr, C125db thd, 21mw at 1msps ltc2389-18 18-bit, 2.5msps sar adc 99.8db snr, C116db thd, 3lsb inl (max) ltc2271 16-bit, 20msps serial dual adc 84.1db snr, 99db sfdr, 92mw per channel references ltc6655 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package LTC6652 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt6200 low noise op-amp 0.95nv/hz, up to 1.6ghz gbw low power, low noise input drive circuit for signals up to 8khz input drive circuit with low distortion up to 1mhz 128k point fft, f smpl = 15msps, f in = 50khz 128k point fft, f smpl = 15msps, f in = 8khz (zoomed view) lt c2387 -18 238718fa 0.1f 50 100 150 200 ?160 ?140 ?120 ?100 ?80 ?60 4.096v ?40 ?20 0 amplitude (dbfs) 238718 ta03b 0v 4.096v 0v in + in ? ltc2387-18 1/2 lt6201 1/2 lt6201 24.9 f in < 1mhz v dd v ddl 5v 2.5v 2.5v ov dd clk dco da 24.9 db twolanes testpat pd cnv refbuf refgnd refin lvds interface 82pf 15mhz sample clock +7.5v -2.5v 238718 ta02 snr = 94.6db thd = ?115db sinad = 94.5db sfdr = 115db 82pf frequency (mhz) 0 2.5 5 7.5 ?160 ?140 ?120 ?100 ?80 0.1f ?60 ?40 ?20 0 amplitude (dbfs) 238718 ta02b 5.1 20 5.1 20 0.1f c1 27nf c2 27nf 10nf 10nf 24.9 24.9 68pf 68pf 0.1f 4.096v 0v 4.096v 0v in + in? ltc2387-18 1/2 lt6237 f in < 8khz 1/2 lt6237 10f c1, c2: grm3195c1h273ja01d or other np0 capacitor +7.5v -2.5v 238718 ta03 snr = 96.0db thd = ?114db sinad = 95.9db sfdr = 116db frequency (khz) 0

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